1. Field of the Invention
The present invention relates to a method for driving a plasma display panel (hereafter, referred to as a PDP).
2. Description of Related Art
PDPs are low-profile display devices which exhibit an excellent visibility, which are capable of performing high-speed display and which are relatively easily achieve large screen display. PDPs of matrix type, especially a surface discharge type, are ones where display electrodes, used in pairs during application of a driving voltage, are arranged on the same substrate. PDPs of this type are suitable for phosphor color display.
As three-electrode surface-discharge color PDPs of an AC type, well-known ones include those disclosed in Japanese Unexamined Patent Publication Nos. HEI 11(1999)-65523, 2001-5423 and 2002-189443. For example, a PDP described in Japanese Unexamined Patent Publication 2002-189443 has a construction as follows: A PDP 10 comprises a front glass substrate 11 and a rear substrate 21, as shown in FIG. 10. On the front substrate 11, sustain electrodes (display electrodes) X and Y are provided on every line L and arranged substantially parallel to each other in a horizontal direction. The line L is a row of cells in the horizontal direction on a screen. The sustain electrodes X and Y are used for generating a surface discharge (a surface discharge is also referred to as a display discharge because it is a main discharge for display, or as a sustain discharge because it is a discharge for sustaining an illuminated state brought about by addressing).
The sustain electrodes X and Y are each formed of a transparent electrode 12 and a metal electrode (bus electrode) 13, and covered with a dielectric layer 17 of a low-melting glass. A protection film 18 of magnesium oxide (MgO) is provided on the surface of the dielectric layer 17.
A plurality of address electrodes A (also referred to as data electrodes) for generating an address discharge are formed on the rear substrate 21. The address electrodes A are covered with a dielectric layer 24. A large number of ribs (barrier ribs) 29 arranged in a stripe pattern are provided on the dielectric layer 24, in parallel to each other in a perpendicular direction (a direction crossing the sustain electrodes) in such a manner that the adjacent ribs sandwich the address electrode A. The ribs 29 partition a discharge space 30 on a subpixel-by-subpixel basis (unit-luminous—area basis) in a line direction and define the height of the discharge space 30.
Three color (R, G and B) phosphor layers 28R, 28G and 28B for color display are respectively provided in elongated grooves between the adjacent ribs. The layout pattern of three colors is a stripe pattern in which cells in one column have the same luminescent color and adjacent columns have different luminescent colors. The discharge space 30 is filled with a discharge gas of a mixture of neon as a main component and xenon, and the phosphor layers 28R, 28G and 28B are locally excited by ultraviolet light emitted by xenon during an electric discharge and emit light.
Each pixel (picture element) for display is constituted by three subpixels along the line L. A structural body within each subpixel is a discharge cell (display element). The ribs 29 are arranged in a stripe pattern as mentioned above and, therefore sections of the discharge space 30 corresponding to the respective columns are each continuous in the column direction across all the lines L. For this reason, the ratio of an inter-electrode spacing between the adjacent lines L (reverse slit) to a surface discharge gap of each line L is selected to be a value which enables discharge coupling to be prevented from generating in a column direction.
Display is performed as follows. A voltage is applied between the sustain electrode Y and the address electrode A so that address discharge is generated and a discharge cell to be lit is selected. Thereafter, a sustain voltage (sustain pulse) is applied to the sustain electrode X and to the sustain electrode Y, alternatively, so that a sustain discharge is generated.
FIG. 11 is a plan view of the PDP shown in FIG. 10. A fundamental minimum unit for light emission in the PDP is a sub-pixel (ordinarily referred to simply as a “discharge cell”) C. One pixel P is composed of three sub-pixels: sub-pixel C (R) for R, sub-pixel C (G) for G, and sub-pixel C (B) for B, arranged side by side in the line direction. Color display in the PDP is performed by varying the level of gradation of each of R, G and B in one pixel P.
FIG. 12 is a diagram illustrating one example of the constitution of a field and driving voltage waveforms in the PDP shown in FIG. 10. For expressing gradation in the PDP by binary control on illumination, a frame F which is a time-sequential input image and is composed of a odd field f and an even field f, is divided into, for example, eight sub-fields sf1, sf2, sf3, sf4, sf5, sf6 sf7 and sf8 (numerical subscripts indicate the order in which the sub-fields are displayed). In other words, each field f is replaced with a group of eight sub-fields sf1 to sf8. The sub-fields sf1 to sf8 are assigned weights of luminance so that relative ratio of luminance in the sub-fields sf1 to sf8 becomes about 1:2:4:8: 16:32:64:128, and the numbers of light emissions in the sub-fields sf1 to sf8 are set according to the weights of luminance.
Since 256 levels of luminance can be set for each of the colors R, G and B by combining illumination and non-illumination on a sub-field basis when one field is composed of eight sub-fields, the number of displayable colors (the number of luminous colors) is 2563. A sub-field period Tsf allotted to each of the sub-fields sf1 to sf8 includes a reset period TR during which charge initialization is carried out in the discharge cells of the entire display screen, an address period TA during which a discharge cell to be lit is selected in the case of, for example, write type addressing, and a sustain period TS during which an illuminated state is sustained for ensuring the luminance according to a gradation level to be produced.
In each sub-field period Tsf, the reset period TR and the address period TA are constant in length regardless of the weight of luminance assigned to the sub-field, while the sustain period TS is longer as the weight of luminance is greater. That means the eight sub-fields Tsf equivalent to one field f are different from one another in length, and the length ratio of a sustain preparation period (=the reset period TR+the address period TA) to the sub-field period Tsf is larger as the weight of luminance is smaller.
Thus, PDPs, which employ a sub-field method for gradation display, and express luminous level according to the number of sustain discharges, have a problem that it is difficult to make fine setting of the weight of luminance by a single sustain discharge. For example, in expressing 256 gradations, it is impossible to make accurate setting the weight of luminance if the total number of sustain discharges is not an integral multiples of 255. Further, in PDPs, the number of gradations displayed, the number of scanning lines, and the luminance (i.e., length of the sustain period TS which is proportional to the number of sustain discharges) are in mutual relation because of a timing constraint on the length of the field f.
Therefore, if the number of scanning lines is large, as in the full-color high-definition PDPs for example, the address period TA is long. However, by reducing the number of light emissions (sustain pulses) to compensate for the long address period Ta, however, luminance declines and screen becomes dark.
In the case where the number of sub-fields is reduced to solve this problem and to obtain high luminance, humans, who are excellent in recognition of gradations, feel roughness and graininess of gradation in dark parts of an image, and thus the quality of display is impaired.
Further, conventional PDPs, compared with other display devices such as a CRT, have a greater gradation ratio of luminance to time, and has a problem in display reliability.